ECEN 248 ECEN248 Lab 9: Counters Clock Dividers and Debounce Circuits – Texas A&M

Description

ECEN 248 ECEN248 Lab 9: Counters Clock Dividers and Debounce Circuits – Texas A&M

Lab 9: Counters, Clock, Dividers, and Debounce Circuits

Objectives:

The purpose of this lab is to help reinforce my knowledge of sequential circuits byintroducing an important synchronous sequential circuit, the binary counter, through the binaryup-counter using familiar combinational components as well as sequential components discussedin the previous lab.

This lab will also demonstrate two more important use cases for binarycounters, namely clock frequency division and I/O debouncing, familiarizing me more withdesigns concepts that will be tested on the FPGA board.

Design:

Exp 1

–Create a new project called lab9.

–Type the Verilog code provided into a source file and save it as ‘clock divider.v’–Connect the logic analyzer to the ZYBO board, as well as the initial setup of the logicanalyzer.

–Ensure that the FPGA board is turned off. Then, locate the JB connector towards thebottom-right of the FPGA board. Open the XDC file and compare it to the diagram inFigure 6, and locate the ClkOut signals of the clock divider.

–Examine the end of the cable, taking note of the individual channel labels. Use thebreadboard and jumper wires to connect the all the ‘GND’ ports on channel 0,1,2,3 to the‘GND’ on JB. Now connect channels 0 through 3 to ClkOut[0] through ClkOut[3] on JBin a similar manner. Have the TA inspect the setup before moving on.

–Turn the logic analyzer on.–Press the Digital button on the front panel

–Press the Channel softkey. Check channels from D0 to D3 and uncheck all the otherchannels, using the Entry knob to choose different channels and press the Entry knob tocheck/uncheck

–Press the Label button. Then press the Channel softkey. Turn the Entry knob to move thehighlight cursor to D0:D0 and select it by pressing the Entry knob.

–Press Enter softkey and then press Spell softkey. Use the Entry knob to select and enterCOUNT2 one character by one character in the New label field. Then press Apply NewLabel softkey to assign channel D0 with a COUNT2 label.

–Repeat the same process to assign a COUNT3 label to D1 channel, a COUNT4 label toD2 channel, and a COUNT5 label to D3 channel.

–Press Run on the logic analyzer once the FPGA has been programmed successfully,should see four separate clock signals on the logic analyzer. Press Auto Scale button oruse the Horizontal Knob to adjust the horizontal scale

–Working with the logic analyzer, press the Cursor button. Use the cursors knob to selectand move the X1 and X2 cursors on the screen, and measure the periods of COUNT2,COUNT3, COUNT4, COUNT5

–Press Digital Button, then press Bus softkey then check Bus1. Then press Channelsoftkey and select D0, D1, D2, D3

ECEN 248 ECEN248 Lab 9: Counters Clock Dividers and Debounce Circuits – Texas A&M

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ECEN 248 ECEN248 Lab 9: Counters Clock Dividers and Debounce Circuits – Texas A&M

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ECEN 248 – Spring 2016 Register Now PreLab 10.pdf Textbook Exercises Fundamentals of Digital Logic with VHDL Design image Fundamentals of Digital Logic with VHDL Design Ch 2, Section EoC End of Chapter, Exercise 2.1Consider the expression x+yz=(x+y)(x+z) .

Consider the left handed term is x+yz and the right…Fundamentals of Digital Logic with VHDL Design Ch 3, Section EoC End of Chapter, Exercise 3.1For a 3 input logic circuit, there are 8 different combinations for which the output can be…

ECEN 248 ECEN248 Lab 9: Counters Clock Dividers and Debounce Circuits – Texas A&M

Fundamentals of Digital Logic with VHDL Design Ch 4, Section EoC End of Chapter, Exercise 4.1Write the truth table for the given function f(x_1,x_2,x_3)=\sum m(1,2,3,5) . Determine the number…Fundamentals of Digital Logic with VHDL Design Ch 5, Section EoC End of Chapter, Exercise 5.1

All positive numbers are called unsigned numbers. The binary number is represented by using the…Fundamentals of Digital Logic with VHDL Design Ch 6, Section EoC End of Chapter, Exercise 6.1Draw a 3 to 8 binary decoder for the given function, f(w_1, w_2, w_3)=\sum m(0, 2, 3, 4, 5, 7) .

It…Fundamentals of Digital Logic with VHDL Design Ch 7, Section EoC End of Chapter, Exercise 7.5Consider the characteristic table of D flip-flop is shown in Table 1. …Fundamentals of Digital Logic with VHDL Design Ch 8, Section EoC End of Chapter, Exercise 8.4The inputs are clock and reset.

The output is z and it consists of 4 bits. According to the states…Fundamentals of Digital Logic with VHDL Design Ch 9, Section EoC End of Chapter, Exercise 9.1Consider that w_{1} and w_{2} are the inputs, y_{1} and y_{2} are the next states, z_{1} and z_{2}…

Fundamentals of Digital Logic with VHDL Design Ch 10, Section EoC End of Chapter, Exercise 10.1The modified shift register circuit in which the parallel-load operation can be performed only when…Fundamentals of Digital Logic with VHDL Design INTRO TO DIGITAL LOGIC

ECEN 248 ECEN248 Lab 9: Counters Clock Dividers and Debounce Circuits – Texas A&M

Tests Questions & Answers Showing 1 to 8 of 26 View all Please see attachments for details 1 2 3 4 5 Please see an attachment for details 1 2 3 4 5 Please see an attachment for details 1 2 3 4 5

Please see an attachment for details 1 2 3 4 5 The attached problems please 1 2 3 4 5 The three attached problems. 1 2 3 4 5 These are simplified equations using boolean algebra can you please help me optimize each one and draw the circuits please. 1 2 3 4 5 Can you please help me simplify each one separately using boolean algebra 1 2 3 4 5

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